Ttgjyuk

Is there a verb for listening stealthily?

How to make an animal which can only breed for a certain number of generations?

IC on Digikey is 5x more expensive than board containing same IC on Alibaba: How?

Is my guitar action too high?

No invitation for tourist visa but I want to visit

Question on Gÿongy' lemma proof

My mentor says to set image to Fine instead of RAW — how is this different from JPG?

What should one know about term logic before studying propositional and predicate logic?

Marquee sign letters

Maximum rotation made by a symmetric positive definite matrix?

"Destructive power" carried by a B-52?

Are there any irrational/transcendental numbers for which the distribution of decimal digits is not uniform?

Pointing to problems without suggesting solutions

Why is there so little support for joining EFTA in the British parliament?

Does the main washing effect of soap come from foam?

How to achieve cat-like agility?

Lemmatization Vs Stemming

Why not use the yoke to control yaw, as well as pitch and roll?

Should man-made satellites feature an intelligent inverted "cow catcher"?

How did 'ликвиди́ровать' semantically shift to mean 'abolish' and 'destroy, kill'?

How to resize main filesystem

How to get a flat-head nail out of a piece of wood?

Random body shuffle every night—can we still function?

How do I find my Spellcasting Ability for my D&D character?

Is there a right way of implementing a T flip flop in verilog wrt using reset signal?

.everyoneloves__top-leaderboard:empty,.everyoneloves__mid-leaderboard:empty,.everyoneloves__bot-mid-leaderboard:empty margin-bottom:0;

1

$begingroup$

I made a t flip flop using structural modeling in verilog.

module Tflip(input T,input clk,output Q,output Qbar) ;
wire S,R;
and(R,Qbar,T,clk);
and(S,Q,T,clk);
SRLatch srt(S,R,Q,Qbar);
endmodule

module SRLatch(input S,input R, output Q, output Qbar);
nand(Q,R,Qbar);
nand(Qbar,S,Q);
endmodule 

And then I tried to make T flip-flop in behavioural modelling. It took me ages to find a neat way to initialise the flip-flop.The below code works great. Is it always required to use a reset of some kind ? Would that make the structural code above wrong?

module T_FF(input T,input rst,input clk,output reg Q);

always@(posedge clk)
begin
if (rst == 1)
Q <= 0;
else if (T)
Q <= !Q;
end
endmodule

I tried to implement a version without a reset signal, but it would only work if the test bench started off a certain way.

Every diagram of T flip-flop i looked for did not show a reset signal, so it took me a lot of time to even understand a reset input was required. It feels like structural modelling a foolproof way of creating things.

verilog flipflop

share|improve this question

asked 1 hour ago

YashaYasha

424

$endgroup$

add a comment | 

1

$begingroup$

I made a t flip flop using structural modeling in verilog.

module Tflip(input T,input clk,output Q,output Qbar) ;
wire S,R;
and(R,Qbar,T,clk);
and(S,Q,T,clk);
SRLatch srt(S,R,Q,Qbar);
endmodule

module SRLatch(input S,input R, output Q, output Qbar);
nand(Q,R,Qbar);
nand(Qbar,S,Q);
endmodule 

And then I tried to make T flip-flop in behavioural modelling. It took me ages to find a neat way to initialise the flip-flop.The below code works great. Is it always required to use a reset of some kind ? Would that make the structural code above wrong?

module T_FF(input T,input rst,input clk,output reg Q);

always@(posedge clk)
begin
if (rst == 1)
Q <= 0;
else if (T)
Q <= !Q;
end
endmodule

I tried to implement a version without a reset signal, but it would only work if the test bench started off a certain way.

Every diagram of T flip-flop i looked for did not show a reset signal, so it took me a lot of time to even understand a reset input was required. It feels like structural modelling a foolproof way of creating things.

verilog flipflop

share|improve this question

asked 1 hour ago

YashaYasha

424

$endgroup$

add a comment | 

$begingroup$

I made a t flip flop using structural modeling in verilog.

module Tflip(input T,input clk,output Q,output Qbar) ;
wire S,R;
and(R,Qbar,T,clk);
and(S,Q,T,clk);
SRLatch srt(S,R,Q,Qbar);
endmodule

module SRLatch(input S,input R, output Q, output Qbar);
nand(Q,R,Qbar);
nand(Qbar,S,Q);
endmodule 

And then I tried to make T flip-flop in behavioural modelling. It took me ages to find a neat way to initialise the flip-flop.The below code works great. Is it always required to use a reset of some kind ? Would that make the structural code above wrong?

module T_FF(input T,input rst,input clk,output reg Q);

always@(posedge clk)
begin
if (rst == 1)
Q <= 0;
else if (T)
Q <= !Q;
end
endmodule

I tried to implement a version without a reset signal, but it would only work if the test bench started off a certain way.

Every diagram of T flip-flop i looked for did not show a reset signal, so it took me a lot of time to even understand a reset input was required. It feels like structural modelling a foolproof way of creating things.

verilog flipflop

share|improve this question

asked 1 hour ago

YashaYasha

424

$endgroup$

module Tflip(input T,input clk,output Q,output Qbar) ;
wire S,R;
and(R,Qbar,T,clk);
and(S,Q,T,clk);
SRLatch srt(S,R,Q,Qbar);
endmodule

module SRLatch(input S,input R, output Q, output Qbar);
nand(Q,R,Qbar);
nand(Qbar,S,Q);
endmodule 

module T_FF(input T,input rst,input clk,output reg Q);

always@(posedge clk)
begin
if (rst == 1)
Q <= 0;
else if (T)
Q <= !Q;
end
endmodule

share|improve this question

asked 1 hour ago

YashaYasha

424

share|improve this question

asked 1 hour ago

YashaYasha

424

asked 1 hour ago

YashaYasha

424

asked 1 hour ago

YashaYasha

424

1 Answer
1

active

oldest

votes

2

$begingroup$

The problem with a T FF is that its state always depends on its previous state. So if you have no way of initializing the state, the simulator will always propagate "unknown" on every clock edge.

Of course, in real life, the TFF will always definitely be in one state or the other, and you often don't care exactly which one it is at any given moment, which is why you see no initialization in typical applications.

share|improve this answer

answered 1 hour ago

Dave Tweed♦Dave Tweed

125k10155269

$endgroup$

add a comment | 

Your Answer

StackExchange.ifUsing("editor", function ()
return StackExchange.using("schematics", function ()
StackExchange.schematics.init();
);
, "cicuitlab");

StackExchange.ready(function()
var channelOptions =
tags: "".split(" "),
id: "135"
;
initTagRenderer("".split(" "), "".split(" "), channelOptions);

StackExchange.using("externalEditor", function()
// Have to fire editor after snippets, if snippets enabled
if (StackExchange.settings.snippets.snippetsEnabled)
StackExchange.using("snippets", function()
createEditor();
);

else
createEditor();

);

function createEditor()
StackExchange.prepareEditor(
heartbeatType: 'answer',
autoActivateHeartbeat: false,
convertImagesToLinks: false,
noModals: true,
showLowRepImageUploadWarning: true,
reputationToPostImages: null,
bindNavPrevention: true,
postfix: "",
imageUploader:
brandingHtml: "Powered by u003ca class="icon-imgur-white" href="https://imgur.com/"u003eu003c/au003e",
contentPolicyHtml: "User contributions licensed under u003ca href="https://creativecommons.org/licenses/by-sa/3.0/"u003ecc by-sa 3.0 with attribution requiredu003c/au003e u003ca href="https://stackoverflow.com/legal/content-policy"u003e(content policy)u003c/au003e",
allowUrls: true
,
onDemand: true,
discardSelector: ".discard-answer"
,immediatelyShowMarkdownHelp:true
);



);

draft saved

draft discarded

Sign up or log in

StackExchange.ready(function ()
StackExchange.helpers.onClickDraftSave('#login-link');
);

Sign up using Google

Sign up using Facebook

Sign up using Email and Password

Post as a guest

Name

Email

Required, but never shown

StackExchange.ready(
function ()
StackExchange.openid.initPostLogin('.new-post-login', 'https%3a%2f%2felectronics.stackexchange.com%2fquestions%2f433825%2fis-there-a-right-way-of-implementing-a-t-flip-flop-in-verilog-wrt-using-reset-si%23new-answer', 'question_page');

);

Post as a guest

Name

Email

Required, but never shown

2

$begingroup$

The problem with a T FF is that its state always depends on its previous state. So if you have no way of initializing the state, the simulator will always propagate "unknown" on every clock edge.

Of course, in real life, the TFF will always definitely be in one state or the other, and you often don't care exactly which one it is at any given moment, which is why you see no initialization in typical applications.

share|improve this answer

answered 1 hour ago

Dave Tweed♦Dave Tweed

125k10155269

$endgroup$

add a comment | 

2

$begingroup$

The problem with a T FF is that its state always depends on its previous state. So if you have no way of initializing the state, the simulator will always propagate "unknown" on every clock edge.

Of course, in real life, the TFF will always definitely be in one state or the other, and you often don't care exactly which one it is at any given moment, which is why you see no initialization in typical applications.

share|improve this answer

answered 1 hour ago

Dave Tweed♦Dave Tweed

125k10155269

$endgroup$

add a comment | 

$begingroup$

The problem with a T FF is that its state always depends on its previous state. So if you have no way of initializing the state, the simulator will always propagate "unknown" on every clock edge.

Of course, in real life, the TFF will always definitely be in one state or the other, and you often don't care exactly which one it is at any given moment, which is why you see no initialization in typical applications.

share|improve this answer

answered 1 hour ago

Dave Tweed♦Dave Tweed

125k10155269

$endgroup$

share|improve this answer

answered 1 hour ago

Dave Tweed♦Dave Tweed

125k10155269

answered 1 hour ago

Dave Tweed♦Dave Tweed

125k10155269

answered 1 hour ago

Dave Tweed♦Dave Tweed

125k10155269